1. Field of the Invention
The present invention relates to a MOS power transistor device.
2. Discussion of the Related Art
MOS power transistors are known to be damaged by exceeding the maximum power dissipatable by the device (and which is constant alongside variations in drain-source voltage), as in the case of shortcircuiting or overloading, which produce a substantial increase in the temperature of the chip integrating the MOS transistors. To overcome this problem, several types of protection have been proposed, none of which, however, have proved entirely effective.
Temperature sensing devices as applied to bipolar power transistors are already known (see, for example, the article by Robert J. Widlar and Mineo Yamatake entitled "Dynamic Safe-Area Protection for Power Transistors Employs Peak-Temperature Limiting", IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 1, February 1987). Such devices consist of a PN junction distributed throughout the bipolar power transistor close to the active emitter. In a typical application described in the above article, the junction is biased by a current source so that the drop at the junction is zero when the limit temperature is reached. An operational amplifier has its input connected to the junction terminals, and, on the limit temperature being exceeded, takes over control of the base circuit of the power transistor to regulate the temperature. Such a solution, however, is not applicable to MOS power transistors.
It is an object of the present invention to provide a MOS power device enabling highly effective protection against overloading and shortcircuiting.